I. Field of the Invention
The present invention relates generally to data processing units and, more particularly, to a functionally complete family of self-timed logic gates.
II. Related Art
As computers are becoming significantly more powerful and substantially minimized in size, the line of demarcation which has historically existed between mainframe computers, minicomputers, and microcomputers has been blurred. Present day minicomputers and microcomputers are as powerful as the mainframe computers of a decade ago. Moreover, the foregoing trend has resulted in an industry-wide demand for computer components which exhibit high performance and occupy less of a computer's valuable real estate.
A major computer component getting much of the attention in the industry is the central processing unit (CPU), which is the primary source of intelligence in a computer. The CPU must be designed to be extremely fast because it generally handles and ultimately supervises most of the interactions which occur within the computer.
The CPU usually has an arithmetic logic unit (ALU) for performing mathematical operations, such as addition, multiplication, and floating point manipulations. Typically, these mathematical operations are implemented via dedicated logic circuits within the CPU. These dedicated logic circuits must be fast, due to their frequent usage, so as not to undesirably slow the overall operation of and interaction with the CPU. Moreover, these dedicated logic circuits must be small in size so as to minimize the overall size of the CPU.
Traditionally, "static" logic gates have been utilized to construct logic circuits for performing mathematical operations. Static logic gates are those which can continuously perform logic operations so long as electrical power is available. In other words, static logic gates need no electrical precharge, or refresh, in order to properly perform logic operations. Static logic gates are functionally complete. They can directly perform both inverting and non-inverting functions. Further, they can be chained together in several stages to collectively perform logic functions. However, static logic gates are undesirably slow individually and, when chained together to collectively perform a logic function, are even slower.
Furthermore, "dynamic" logic gates are known in the art. Dynamic logic gates are used in the conventional design of logic circuits which require high performance and modest size. Dynamic logic gates are those which require a periodic electrical precharge, or refresh, such as with a dynamic random access memory (DRAM), in order to maintain and properly perform its intended logic function. Once an electrical precharge supplied to a dynamic logic gate has been discharged by the dynamic logic gate, the dynamic logic gate can no longer perform another logic function until subsequently precharged.
However, the use of conventional dynamic logic circuits in the construction of logic networks is problematic. They suffer from functional incompleteness. In other words, only non-inverting logic functions can be performed with the conventional dynamic logic gates. Moreover, high performance adder logic circuits and multiplier logic circuits invariably require logic inversions. Consequently, adder logic circuits and multiplier logic circuits cannot be built from conventional dynamic logic gates.
Furthermore, in many instances, conventional dynamic logic gates cannot be directly connected together as successive stages to collectively perform logic functions and still maintain their proper dynamic nature. Specifically, problems in regard to "static hazards" arise. A static hazard is an inherent condition which occurs in combinational logic configurations as a result of propagation delays.
For example, consider a two-input exclusive OR gate in a conventional binary logic system when both inputs are high and then both concurrently turn low. From a computer programmer's perspective, the output of the exclusive OR gate should remain low before, during, and after the transition. In reality, one of the inputs will change just before the other. Consequently, the output of the exclusive OR gate will undesirably and suddenly bounce high then low during the transition time.
Static hazards usually do not pose a substantial problem in a chain of static logic circuits, because the static logic circuits can respond more than once so as to be in proper accord with the ultimate states of the logic inputs. However, in a chain of dynamic logic circuits having an odd number of inversions in a logic path, static hazards will result in logic errors because the dynamic logic circuits, once triggered, cannot further respond until subsequently precharged. Hence, dynamic logic circuits cannot effectively be connected together in stages to derive some logic gates and still maintain their dynamic nature because they cannot recover from inherent static hazards.